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W83194AR-96
200MHZ CLOCK FOR WHITNEY CHIPSET 1.0 GENERAL DESCRIPTION
The W83194AR-96 is a Clock Synthesizer for Intel Whitney chipset. W83194AR-96 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 32 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194AR-96 provides I C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% center and 0-0.5% down type spread spectrum to reduce EMI. The W83194AR-96 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
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1.0 PRODUCT FEATURES
* * * * * * * * * * * * 2 CPU clocks 9 SDRAM clocks for 2 DIMMs 8 PCI synchronous clocks. Optional single or mixed supply: (VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz 2 2 I C 2-Wire serial interface and I C read back 0.25% or 0.5% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz for USB 24 MHz for super I/O Packaged in 48-pin SSOP
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 3.0 PIN CONFIGURATION
REF1/*APIC_SEL VDDR Xin Xout VSS VSS 3V66-0 3V66-1 VDD3 VDDP PCICLK0/ FS0# PCICLK1/ FS1# PCICLK2/*SEL24_48# VSS PCICLK3/ FS4# PCICLK4 PCICLK5 VDDP PCICLK6 PCICLK7 VSS PD# *SDCLK *SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddA IOAPIC VDDC CPUCLK0 CPUCLK1 VSS VSS SDRAM 0 SDRAM 1 SDRAM 2 VDDS SDRAM 3 SDRAM 4 SDRAM 5 VSS SDRAM 6 SDRAM 7 SDRAM_F VDDS VSS 24_48MHz/ FS2# 48MHz-0 48MHz-1/ FS3# VDD48
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 4.0 FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) CPU /SDRAM 3V66 (MHz) PCI(MHz) IOAPIC (MHz) IOAPIC (MHz) APIC_SEL=1 APIC_SEL=0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
66.8 90 100.2 72 133.6 95.25 133.6 124 119 114 110 105 83.3 75 89.07 121 135 125 127 130 140 136 166 155 150 117 107 100.9 145 140 138 137
100.2 90 100.2 108 133.6 95.25 100.2 124 119 114 110 105 124.95 112.5 133.6 121 101.25 125 127 130 140 136 166 155 112.5 117 107 100.9 108.75 105 103.5 102.75
2/3 1 1 2/3 1 1 4/3 1 1 1 1 1 2/3 2/3 2/3 1 4/3 1 1 1 1 1 1 1 4/3 1 1 1 4/3 4/3 4/3 4/3
66.80 60.00 66.80 72.00 66.80 63.50 66.80 82.67 79.33 76.00 73.33 70.00 83.30 75.00 89.07 80.67 67.50 83.33 84.67 86.67 70.00 68.00 83.00 77.50 75.00 78.00 71.33 67.27 72.50 70.00 69.00 68.50
33.40 30.00 33.40 36.00 33.40 31.75 33.40 41.33 39.67 38.00 36.67 35.00 41.65 37.50 44.53 40.33 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50 34.25
16.70 15.00 16.70 18.00 16.70 15.88 16.70 20.67 19.83 19.00 18.33 17.50 20.83 18.75 22.27 20.17 16.88 20.83 21.17 21.67 17.50 17.00 20.75 19.38 18.75 19.50 17.83 16.82 18.13 17.50 17.25 17.13
33.40 30.00 33.40 36.00 33.40 31.75 33.40 41.33 39.67 38.00 36.67 35.00 41.65 37.50 44.53 40.33 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50 34.25
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 5.0 SERIAL CONTROL 0REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
Frequency Table Setting by I2C (SEL5 ~ SEL0)
SSE L5 SS EL4 SS EL3 SS EL2 SS EL1 SS EL0 CPU (MHz) SDRAM (MHz) CPU/SD RAM 3V66 (MHz) PCI (MHz) IOAPIC (MHz) APIC_SEL=1 IOAPIC (MHz) APIC_SEL=0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
66.8 90 100.2 72 133.6 95.25 133.6 124 119 114 110 105 83.3 75 89.07 121 135 125 127 130 140 136 166 155 150 117 107 100.9 145 140 138 137
100.2 90 100.2 108 133.6 95.25 100.2 124 119 114 110 105 124.95 112.5 133.6 121 101.25 125 127 130 140 136 166 155 112.5 117 107 100.9 108.75 105 103.5 102.75
2/3 1 1 2/3 1 1 4/3 1 1 1 1 1 2/3 2/3 2/3 1 4/3 1 1 1 1 1 1 1 4/3 1 1 1 4/3 4/3 4/3 4/3
66.80 60.00 66.80 72.00 66.80 63.50 66.80 82.67 79.33 76.00 73.33 70.00 83.30 75.00 89.07 80.67 67.50 83.33 84.67 86.67 70.00 68.00 83.00 77.50 75.00 78.00 71.33 67.27 72.50 70.00 69.00 68.50
33.40 30.00 33.40 36.00 33.40 31.75 33.40 41.33 39.67 38.00 36.67 35.00 41.65 37.50 44.53 40.33 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50 34.25
16.70 15.00 16.70 18.00 16.70 15.88 16.70 20.67 19.83 19.00 18.33 17.50 20.83 18.75 22.27 20.17 16.88 20.83 21.17 21.67 17.50 17.00 20.75 19.38 18.75 19.50 17.83 16.82 18.13 17.50 17.25 17.13
33.40 30.00 33.40 36.00 33.40 31.75 33.40 41.33 39.67 38.00 36.67 35.00 41.65 37.50 44.53 40.33 33.75 41.67 42.33 43.33 35.00 34.00 41.50 38.75 37.50 39.00 35.67 33.63 36.25 35.00 34.50 34.25
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY
SSE L5 SS EL4 SS EL3 SS EL2 SS EL1 SS EL0 CPU (MHz) SDRAM (MHz) CPU/SD RAM 3V66 (MHz) PCI (MHz) IOAPIC (MHz) APIC_SEL=1 IOAPIC (MHz) APIC_SEL=0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
136 138 139 141 142 142 143 143 144 144 146 146 147 147 148 148 149 152 153 156 157 158 159 160 162 164 170 175 180 185 190 200.4
102.00 138.00 104.25 141.00 142.00 106.50 143.00 107.25 144.00 108.00 146 109.50 147 110.25 148.00 111.00 111.75 152.00 114.75 156.00 117.75 158.00 119.25 160.00 121.5 164.00 170.00 175 120 92.5 126.67 133.60
4/3 1 4/3 1 1 4/3 1 4/3 1 4/3 1 4/3 1 4/3 1 4/3 4/3 1 4/3 1 4/3 1 4/3 1 4/3 1 1 1 2/3 2 3/2 3/2
68.00 69.00 69.50 70.50 71.00 71.00 71.50 71.50 72.00 72.00 73.00 73.00 73.50 73.50 74.00 74.00 74.50 76.00 76.50 78.00 78.50 79.00 79.50 80.00 81.00 82.00 85.00 87.5 60 61.67 63.33 66.80
34.00 34.50 34.75 35.25 35.50 35.50 35.75 35.75 36.00 36.00 36.50 36.50 36.75 36.75 37.00 37.00 37.25 38.00 38.25 39.00 39.25 39.50 39.75 40.00 40.50 41.00 42.50 43.75 30 30.83 31.67 33.40
17.00 17.25 17.38 17.63 17.75 17.75 17.88 17.88 18.00 18.00 18.25 18.25 18.38 18.38 18.50 18.50 18.63 19.00 19.13 19.50 19.63 19.75 19.88 20.00 20.25 20.50 21.25 21.88 15 15.42 15.83 16.70
34.00 34.50 34.75 35.25 35.50 35.50 35.75 35.75 36.00 36.00 36.50 36.50 36.75 36.75 37.00 37.00 37.25 38.00 38.25 39.00 39.25 39.50 39.75 40.00 40.50 41.00 42.50 43.75 30 30.83 31.67 33.40
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 5.1 Register 0: CPU Frequency Select Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 2 SSEL3 (Frequency table selection by software via I C ) 2 SSEL2 ( Frequency table selection by software via I C) 2 SSEL1 ( Frequency table selection by software via I C) 2 SSEL0 ( Frequency table selection by software via I C) 0 = Selection by hardware 2 1 = Selection by software I C - Bit (2, 7:4), Register1 Bit1 2 SSEL4 (Frequency table selection by software via I C ) 2 SSEL5 (Frequency table selection by software via I C ) 0 = Running 1 = Tristate all outputs
5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp X X X 1 1 1 1 0 Pin 28 27 26 Description FS3# FS0# FS2# 24_48MHz(Active / Inactive) 48MHz-0(Active / Inactive) 48MHz-1(Active / Inactive) 1 = 0.25% Center type Spread Spectrum Modulation 0 =0.5% Center type Spread Spectrum Modulation 0 = Normal 1 = Spread Spectrum enabled
5.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 32 33 35 36 37 39 40 41 SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) Description
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY
5.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 20 19 17 16 15 13 12 11 PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description
5.5 Register 4: Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp X 1 1 X 1 X 1 1 Pin 7 8 47 44 45 APIC_SEL# 3V66_0(Active / Inactive) 3V66_1(Active / Inactive) FS4# IOAPIC (Active / Inactive) FS1# CPUCLK1(Active / Inactive) CPUCLK0(Active / Inactive) Description
5.6 Register 5: Reserve Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 0 0 Pin Description SKEW2(SDRAM to CPU Skew programming bit) SKEW1(SDRAM to CPU Skew programming bit) SKEW0(SDRAM to CPU Skew programming bit) SDRAM_F Reserve Reserve Reserve Reserve
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 5.7 Register 6: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 1 0 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description
5.8 Register 7: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 0 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Description
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 6.0 SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65C to + 150C - 55C to + 125C 0C to + 70C
6.2 AC CHARACTERISTICS
VddR=Vdd3=VddP=VddS=3.3V 5 %, VddC = VddA= 2.375V~2.9V , TA = 0C to +70C Parameter Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion VRBE 0.7 2.1 V tTLH tTHL Vover 0.7 1.5 V 0.4 1.6 ns 15 pF Load on CPU and PCI outputs 22 at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. BWJ 500 KHz tJA 500 ps tOFF tSKEW tCCJ Symbol Min 45 1 Typ 50 Max 55 4 250 250 Units % ns ps ps Test Conditions Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY
6.3 DC CHARACTERISTICS
VddR=Vdd3=VddP=VddS=3.3V 5 %, VddC = VddA= 2.375V~2.9V , TA = 0C to +70C Parameter Input Low Voltage Input High Voltage Input Low Current (no pull-up Resistors) Input Low Current (pull-up Resistors) Input High Current Operating Current Power Down Current Input Frequency Pin Inductance Input Capacitance Symbol VIL VIH IIL IIL IIH IDD IDDPD Fi Lpin CIN COUT CINX TTra T TSTA Min Vss0.3 2.0 -5 -200 -5 60 400 14.318 7 5 6 13.5 1 22.5 3 10 3 2.0 -100 5 100 600 Typ Max 0.8 Vdd +0.3 Units Vdc Vdc A A A mA A MHz nH pF pF pF mS nS mS @66M CL= 0pF Vdd=3.3V Logic Inputs Output pins capacitance X1 & X2 pins Test Conditions
Transition Time Disable/Enable Delay Clock stabilization
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY 7.0 ORDERING INFORMATION
Part Number W83194AR-96 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
8.0 HOW TO READ THE TOP MARKING
W83194AR-96 28051234 814GAB
1st line: Winbond logo and the type number: W83194AR-96 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: July 1999 Revision 0.35
W83194AR-96
PRELIMINARY
9.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: July 1999 Revision 0.35

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